The present invention relates to a frequency conversion circuit.
A frequency conversion circuit is an essential circuit in a receiver. In a frequency conversion circuit, the non-linear characteristic of an active element such as a transistor is utilized to convert two signals of other frequencies.
An example of a frequency conversion circuit is shown in FIG. 1. Two signals A and B respectively having different frequencies f.sub.A and f.sub.B are applied respectively through d.c. blocking capacitors C.sub.1 and C.sub.2 to the base of a bipolar transistor Q.sub.1, which is a non-linear characteristic active element. An output signal C having a desired frequency f.sub.C is provided at the collector load of the transistor, specifically, a collector tuning circuit composed of a capacitor C.sub.3 and a transformer T.sub.1. A power source E.sub.1 and a resistor R.sub.1 provide base bias for the transistor Q.sub.1.
The input and output characteristic of the transistor Q.sub.1 can be represented by the following equation: EQU v.sub.o =a.sub.1 v.sub.i +a.sub.2 v.sub.i.sup.2 +a.sub.3 v.sub.i.sup.3 +(1)
where a.sub.1, a.sub.2, a.sub.3, . . . are constants, v.sub.i is the input signal, and v.sub.o is the output signal.
The case where a desired signal of frequency f.sub.d1 and interference signals of frequencies f.sub.1 and f.sub.2 which are close to f.sub.d1, as shown in FIG. 2, are applied to the transistor circuit having the above-described construction will be considered. If it is assumed that the frequencies of the interference signals are: f.sub.1 =f.sub.d1 +.DELTA.f and f.sub.2 =f.sub.d1 +2.DELTA.f, respectively, then signals having frequencies mf.sub.1 .+-.nf.sub.2 (where m and n are integers) are outputted. For m=2 and n=1, the following equation can be written: EQU 2f.sub.1 -f.sub.2 =2(f.sub.d1 +.DELTA.f)-(f.sub.d1 +2.multidot..DELTA.f)=f.sub.d1. (2)
That is, because of the non-linear characteristic operation of the transistor, an interference signal having the same frequency f.sub.d1 as that of the desired signal is produced from the two interference signals f.sub.1 and f.sub.2.
If m=-1 and n=2, the following equation can be written: EQU 2f.sub.2 -f.sub.1 =f.sub.d1 +3.multidot..DELTA.f=f.sub.d2. (3)
Thus, in receiving the second desired signal f.sub.d2, an interference signal having the same frequency as that of the desired signal is produced. The production of intermodulation (IM) interference signals in the cases of m=2, n=1 and m=-1, n=2 is attributed to the odd order terms of equation (1).
In the circuit of FIG. 1, the collector tuning circuit (C.sub.3 and T.sub.1) operates to select one of the signal frequencies f.sub.A +f.sub.B corresponding to the second order term in equation (1).
The circuit of FIG. 1 is disadvantageous in that, upon reception of the above-described interference signals f.sub.1 and f.sub.2, the desired signal f.sub.d1 =f.sub.A .+-.f.sub.B is subjected to IM (intermodulation) interference. In the conventional circuit, as long as the transistor Q.sub.1 has an input and output characteristic including the aforementioned odd order terms, the occurrence of IM (intermodulation) interference is unavoidable.